This invention relates to decimal floating point multiplication, and more particularly, to a floating point multiplier that utilizes a pipelined decimal adder.
As the speed of microprocessors continues to increase, the amount of computation that can be done in a single cycle decreases. For decimal floating point operations the carry chain for the wide adder prevents a full addition from being computed in a single cycle. One solution to prevent the decimal adder from limiting the performance of the computer system is to break the addition into two separate steps. Note that the IEEE 754R Standard defines two formats for decimal floating-point numbers, a doubleword format that contains a 16 digit coefficient and a quadword format that contains a 34 digit coefficient. Both formats also contain an exponent field and a sign bit.
Implementing a decimal multiplication operation with a two cycle adder creates complications for a multiplication algorithm. The multiplication will take twice as many clock cycles because the two cycle adder requires twice as many clock cycles. It would be desirable to be able to perform the multiplication in fewer clock cycles while still being able to utilize a two cycle adder. It is necessary to compute at least one partial product per cycle. The invention disclosed herein includes an algorithm for decimal multiplication that maintains the desired performance of an average of one partial product computation per cycle using a two cycle adder.